I. Field of the Invention
The present invention is related to the field of analog-to-digital converter (ADC) technology, and more particularly, to a continuous integrating ADC which has a residue ADC for optimizing speed and resolution.
II. Related Art
Integrating ADCs, as opposed to other types of ADCs, have been used in the art because of their ability to make high-resolution measurements. However, integrating ADCs have been relatively slow historically. Numerous attempts have been made to increase the speed of such integrating ADCs without adversely affecting the resolution of their outputs. But, such efforts have had only limited success because the speed of the integrating ADCs is generally inversely proportional to the resolution of the output. In other words, in integrating ADCs, speed has generally been traded off for resolution.
A traditional integrating ADC is illustrated in FIG. 1. Generally, the integrating ADC converts an unknown input voltage V.sub.IN into a digital signal, known in the art as an "integrator count." An integrator 102 is comprised of an operational amplifier (op-amp) 104 and a parallel capacitor C.sub.1. The integrator 102 receives the unknown input voltage V.sub.IN and provides an integrator output voltage V.sub.INT to a comparator 108. The comparator 108 compares V.sub.INT to a reference voltage, which oftentimes is ground, as shown in FIG. 1. The comparator 108 then feeds a comparator output voltage V.sub.C to the control logic 110, which in turn controls a switch SW1. The switch SW1 is controlled to provide either the input voltage V.sub.IN or a reference voltage V.sub.REF at any given instance. The reference voltage V.sub.REF can be any means for providing charge to the integrator 102. The reference voltage V.sub.REF can be positive or negative and can even be a current source, instead of a voltage source as shown. Further, the control logic 110 outputs the slope count, as indicated at a line 114.
Historically, a technique known as dual slope integration has been employed by traditional integrating ADCs, as shown in FIG. 1, in order to generate a digital output. Specifically, the unknown input voltage V.sub.IN is applied to the integrator 102 for a so-called "run-up" (RU) interval of duration T, as illustrated in FIG. 2. The input voltage V.sub.IN is then disconnected and, at the same time, a reference discharging voltage V.sub.REF is applied to the integrator 102 during a so-called "run-down" (RD) interval. The RD interval ends when the capacitor C.sub.1 is totally discharged and, accordingly, the integrator output voltage V.sub.INT is zero.
The duration t of the RD interval is measured, and the value of the unknown input voltage V.sub.IN is computed as follows: V.sub.IN =tx(V.sub.REF /T). The value of duration t is typically measured by counting (usually synchronous with the clock) during the RD interval. For a given count, the sensitivity of the ADC increases with a decrease in the rate at which the discharge occurs. Therefore, sensitivity can be increased by decreasing the magnitude of V.sub.REF. However, the decrease V.sub.REF results in a slower response of the circuit, which is impractical in many instances.
The sensitivity can also be increased by increasing the maximum voltage V.sub.M of the integrator output voltage V.sub.INT for a fixed duration of the RU interval. An increase in the maximum integrator output voltage V.sub.M is achieved by reducing the value of the input resistance R.sub.IN to increase the slope of the integrator output voltage V.sub.INT during the RU interval. However, for an op-amp integrator 102, the integrator output voltage V.sub.INT must be within the bounds of the op-amp power supply voltage limits.
In order to maintain high sensitivity and, at the same, time increase the response time of an integrating ADC, a technique known as "multisloping" has been devised by those skilled in the art. U.S. Pat. No. 4,357,600 to Ressmeyer, which is incorporated herein by reference, describes the use of multisloping for producing a digital manifestation of an unknown input voltage V.sub.IN.
Generally, multisloping can be employed during both the RU and RD intervals. Essentially, multisloping is a modification of the dual-slope integration wherein the integrating ADC is allowed to have an effective voltage swing much larger than the physical limitations of the integrator circuit hardware. The multisloping technique involves periodically applying a positive and/or negative reference voltage V.sub.REF to the integrator input so that the charge from the unknown input voltage V.sub.IN plus the charge from the reference voltage V.sub.REF is never large enough to saturate the integrator 102. By accounting for the total amount of reference charge transferred to the integrator 102 during the RU and RD intervals, the digital output of the integrating ADC can be measured with much higher accuracy and resolution. To account for the total amount of reference charge transferred to the integrator 102, so-called "slope counts" can be preformed, as will be discussed in detail further below. Essentially, the "slope count" is the number of time intervals during which the integrator 306 is ramping positive minus the number of time intervals during which the integrator 306 is ramping negative.
Although the multisloping technique allows for improved resolution, the resulting time period for a reading may still be quite great for a high resolution output. For example, about 150 microseconds could be required to perform multislope run-down alone for a resolution of about six digits. Moreover, dedicated high-speed logic must be used for this purpose as well as custom-integrated circuitry which is quite expensive. It is thus desirable to shorten the time period for the RD interval so that speed can be improved and so that the ADC is more cost-effective without sacrificing resolution and linearity.
Copending application, Ser. No. 07/446,232, entitled "Integrating Analog to Digital Converter," filed Dec. 15, 1989, by R. Riedel, teaches a technique for substantially minimizing the RD interval via the addition of a conventional ADC to the integrator. The additional ADC measures the residual integrator output voltage V.sub.INT-RES which remains after the RU interval. The residual integrator output voltage V.sub.INT-RES is then converted into a fractional part of a slope count and added to the slope counts derived during the RU interval. As a result, the resolution and speed of the integrating ADC is enhanced.
FIG. 3 substantially represents the embodiment taught by Riedel. As shown in FIG. 3, an integrating ADC 300 has an integrator 306, a comparator 308, a logic/control circuit 310, and a residue ADC 312. During operation, initially, switch SW4 is closed, switch SW3 is open, and the output of the integrator 306 is at zero. To begin a measurement, or "reading", switch SW4 is opened, switch SW3 is closed, and switches SW1, SW2 are opened by logic/control circuit 310. The output of the integrator 306 then begins to ramp positive as shown in Waveforms 1-3 of FIG. 4, due to the input voltage V.sub.IN in combination with the current source I.sub.3. The integrator 306 is instructed by logic/control circuit 310 to ramp positive for a duration T/2, as shown, so that run-up always starts in the same direction. After a time period T/2, switches SW1, SW2 are closed, and the integrator 306 begins to ramp negative at a rate determined by the relative values of input voltages of V.sub.IN, resistance R.sub.IN, and the currents I.sub.1, I.sub.2, and I.sub.3, where I.sub.1 =I.sub.2 =I.sub.3.
After another time period T, the comparator output voltage V.sub.c of the comparator 308 is sampled. If the comparator output voltage V.sub.c is negative, switches SW1, SW2 are opened, and the integrator 306 again begins to ramp positive, as shown in Waveform 1 of FIG. 4. On the other hand, if the comparator output voltage V.sub.c is positive, switches SW1, SW2 are maintained closed, and the integrator 306 continues to ramp negative, as shown in Waveform 3 of FIG. 4. The foregoing process continues for as many time periods T as desired for the required resolution. The more time periods T used, the greater the resolution.
As is apparent from FIG. 4, the integrator output voltage Waveforms 1-3 are dependent upon the sign and magnitude of the input voltage V.sub.IN. For example, Waveform 1 of FIG. 4 shows the response for a positive input voltage V.sub.IN whereby the integrator 306 slopes negative at a faster rate than the integrator 306 ramps positive, due to the inverting effect of the integrator 306. As a result, the overall slope count is positive. The slope count is the number of time intervals of duration T during which the integrator 306 is ramping positive minus the number of intervals of duration T during which the integrator 306 is ramping negative.
The integrator output voltage Waveform 2 of FIG. 4, on the other hand, illustrates the resulting slope for an input voltage V.sub.IN =0. The resulting slope count is equal to zero because the integrator 306 ramps at the same rate in the positive and negative directions.
Finally, the integrator output voltage resulting from a negative input voltage V.sub.IN is illustrated in Waveform 3 of FIG. 4. For a negative input voltage V.sub.IN, the integrator 306 ramps positive at a greater rate than the integrator 306 ramps negative, so that a negative slope count results. Thus, the integrator output has a steeper slope in a given direction in accordance with the magnitude of the input voltage V.sub.IN, while the direction is determined at comparator 308 in accordance with the sign of the input voltage V.sub.IN.
Hence, as previously described, a measure of the magnitude of the input voltage V.sub.IN may be obtained by computing the number of time durations T during which the comparator 308 exhibits a negative output (or, equivalently, the integrator is ramping positive) minus the number of time durations T during which the comparator 308 exhibits a positive output (or, equivalently, the integrator is ramping negative). Logic/control circuit 310 then samples the comparator output voltage V.sub.c of comparator 308 and computes the slope count. The slope count is used as the most significant digit part of the total ADC reading.
The unknown input voltage V.sub.IN is measured in the foregoing manner during the RU interval to a resolution determined by the number of time periods T in the measurement cycle. For example, 100 time periods T would imply a resolution of one part in 100, and of course, as the number of time periods T during run-up is increased, the output resolution is correspondingly increased.
During the RD interval, the residue ADC 312 functions as a successive approximation converter for calculating the residual integrator voltage V.sub.INT-RES remaining after the RU interval. Specifically, at the end of the RU interval, switches SW2, SW3 are opened. The integrator 306 is thus in a balanced state of input, and the output remains constant, at least for a short time period, as shown at the far right of integrator output voltage Waveforms 1-3 of FIG. 4.
As shown in FIG. 4, the integrator output voltage V.sub.INT will not necessarily be at zero volts at the end of the RU interval and will ordinarily vary from zero depending on the exact value of the input voltage V.sub.IN. The remaining voltage is shown in FIG. 4 as a residual integrator voltage V.sub.INT-RES. The least significant bits of the ADC digital output can be computed by precisely measuring the residual integrator voltage V.sub.INT-RES at the end of the RU interval.
The residual integrator voltage V.sub.INT-RES is converted into a fractional number of a slope count via a complex equation described by Riedel. The total slope count is equal to the sum of (1) the fractional number of slope counts derived from the residual integrator voltage V.sub.INT-RES and (2) the difference between the positive and negative slope counts derived during the RU interval.
In conclusion, the ADC 300 taught by Riedel provides for high speed and high resolution digital-to-analog conversions. However, the integrator 306 must be zeroed, or initialized, by the switch SW4 at the beginning of each count, and the input voltage V.sub.IN must be periodically switched off. In other words, although the ADC 300 taught by Riedel does not proceed through the entire RD interval, the ADC 300 must at least enter the RD interval in order to measure the residual integrator voltage V.sub.INT-RES. The foregoing methodology is not optimal in terms of speed.